Best Motherboard for a Dual-GPU Local LLM Build (2026): PCIe Lanes, x8/x8 vs x16/x4, and What Actually Costs You Tokens/sec

You have decided on local AI. You have picked your two cards — probably a pair of used RTX 3090s for 48GB on a budget, or two RTX 5090s if the budget is not the constraint. And now you are stuck on the board, because consumer AM5 gives you 24 usable PCIe lanes, every forum answer contradicts the last one, and the affiliate roundups that rank for this query are spec tables with no methodology behind them.

This post answers the question underneath the question: does the slot configuration change my tokens per second, and by how much? The honest answer will save most readers a four-figure platform upgrade.

1. The Short Answer: Three Boards, Three Budgets

Three platform tiers cover essentially every dual-GPU local-LLM build. Pick the row that matches your engine and your cards, then read the rest to understand why.

Board price bands are street-price observations as of 19 September 2026 and are volatile in the current component-pricing environment — see the 2026 DRAM shortage analysis for why. Slot and lane configurations are per-board, not per-chipset: always confirm against the specific manual. Reference boards for the two upper tiers are the ASUS Pro WS TRX50-SAGE WIFI and the ASUS Pro WS WRX90E-SAGE SE, whose documentation lists the lane allocation explicitly.

If you are still deciding whether two GPUs is even the right shape of machine, our multi-GPU local LLM setup guide is the parent article to this one — it covers the software side; this post covers the slot it plugs into.

2. The Thing Nobody Tells You: PCIe Bandwidth Barely Matters for Inference

The reason is structural. A transformer generates a token by streaming every weight it needs through the GPU's own memory system. On an RTX 5090 that is 1,792 GB/s of GDDR7 bandwidth, entirely on-card. The PCIe bus is not in that loop. What crosses the bus during a chat session is the prompt going in and the generated tokens coming back — a few kilobytes. A PCIe 4.0 x4 link moves roughly 8 GB/s. You are using a rounding error of it.

Where bus bandwidth genuinely shows up: load time

The one place a narrow link is visible on a single-GPU system is moving weights from storage into VRAM at startup. Here is the arithmetic for a 24GB GGUF checkpoint — roughly a 70B model at 4-bit quantization, or a 32B at 8-bit:

Figures are theoretical peak from PCIe encoding rates (~3.94 GB/s per lane at Gen5, ~1.97 GB/s at Gen4), not measured throughput; real transfers run below them. Loads also pass through the page cache and the CPU, so treat these as floors.

Read that table carefully, because the conclusion is the opposite of what the roundups imply: at every tier above PCIe 4.0 x4, your storage is the constraint, not your slot. A Gen4 NVMe drive at ~7 GB/s sequential read takes about 3.4 seconds to stream 24GB; a Gen5 drive at ~14 GB/s takes about 1.7. Both numbers dwarf the difference between an x8 and an x16 slot. If model load time annoys you, buy a faster drive — our NVMe guide for local AI covers which one — and stop shopping for lanes.

This holds at the top of the stack too. An RTX 5090 at $1,999–$2,199 lists a PCIe 5.0 x16 interface and 32GB of GDDR7, but a single one of those cards running a 32B model in VRAM does not care whether it got eight lanes or sixteen. Rost Glukhov's write-up "LLM Performance and PCIe Lanes: Key Considerations" is the most rigorous public treatment of this and reaches the same conclusion: after load, a narrow link is sufficient for single-GPU generation.

A note on what public data does not cover. Argonne National Laboratory's LLM-Inference-Bench (arXiv 2411.00136) is the strongest peer-reviewed benchmarking work in this space, spanning frameworks and accelerators — and it does not isolate PCIe link width as a variable. Neither does the vLLM or ROCm benchmark documentation. Every specific percentage you will find quoted for "x8/x8 vs x16/x4 token generation" traces back to an affiliate page with no stated methodology. We are not repeating those numbers, and neither should anyone else.

3. Where It DOES Matter: Tensor Parallelism vs Layer Splitting

This is the distinction that makes everything else in the post make sense, and no competing page draws it. Two GPUs can share a model in two fundamentally different ways, and they place completely different demands on the bus.

llama.cpp and Ollama use pipeline (layer) parallelism by default. GPU 0 owns layers 0–39, GPU 1 owns 40–79, and exactly one activation tensor crosses the bus at the handoff. That tensor is a few megabytes. A PCIe 4.0 x4 link at ~8 GB/s handles that thousands of times over. It is why so many r/LocalLLaMA builders report dual-3090 rigs running happily on a consumer board with one card on a chipset-fed x4 slot — community reports rather than benchmark data, but consistent and numerous.

vLLM with --tensor-parallel-size 2 does model sharding instead: every attention and MLP weight matrix is split column-wise or row-wise across both cards, and each partial result must be all-reduced before the next layer runs. For an 80-layer model generating 30 tokens per second, that is 2,400 synchronisation events per second across the bus. Red Hat's developer write-up "llama.cpp vs. vLLM: Choosing the right local LLM inference engine" (June 2026) is the cleanest vendor-neutral treatment of why the two engines behave so differently here.

The payoff for that traffic is real: tensor parallelism keeps both GPUs computing simultaneously, so it scales throughput and cuts latency, where layer splitting mostly just adds capacity. That is the trade. You are buying concurrency with bandwidth.

The decision rule: if your stack is Ollama or LM Studio, buy the consumer board. If your stack is vLLM serving concurrent requests, budget for lanes. Most people reading this are in the first group and do not know it yet.

4. The Lane Budget, Honestly: AM5 vs Threadripper vs Threadripper PRO

Your CPU choice is the lane budget — the chipset only redistributes what the CPU provides. Here is what each platform actually gives you.

Lane counts are from AMD Socket AM5 / sTR5 platform documentation, Intel Z890 platform documentation, and ASUS Pro WS TRX50-SAGE WIFI / Pro WS WRX90E-SAGE SE product documentation. Platform cost is CPU + board + RAM at 19 September 2026 street pricing; DDR5 in particular is moving fast.

Sit with the AM5 row for a second, because it is the one that catches people. Twenty-four lanes is the entire budget. The moment you bifurcate the graphics x16 into x8/x8, there is nothing left over — the primary M.2 keeps its four lanes, the chipset keeps its four, and every additional M.2 socket and every USB4 controller on the board is fed through that single four-lane chipset uplink. It works. It is not generous. Add a fast capture card or a 10GbE NIC and you are contending for chipset bandwidth.

And that is the honest framing of the upgrade: a TRX50 platform costs roughly $1,800–$2,900 more than AM5 before you buy a single graphics card, and a WRX90 platform more again. What you get for it is x16/x16, quad- or eight-channel memory bandwidth, ECC, and lanes you are not rationing. What you do not get is faster layer-split inference. For a large share of buyers, that money converts far better into a second RTX 3090 or a step up to a 4090.

One genuine reason to consider HEDT anyway: system RAM capacity and channel count. If your plan involves MoE models with CPU offload, quad-channel changes the arithmetic in a way lanes do not — see how much RAM local AI actually needs and running large MoE models on a small GPU.

5. x8/x8 vs x16/x4 — The Configuration That Actually Bites

The failure mode is not x8. x8/x8 is a clean, symmetric, well-supported configuration and it is what a good consumer board gives you when it bifurcates properly.

The failure mode is a board that silently drops the second x16-length slot to x4 — or disables it entirely — because the lanes went somewhere else. This is not a defect; it is documented behaviour that almost nobody reads. Lane allocation varies by board and by which M.2 sockets are populated, and the place it is written down is a footnote table in the manual, not the marketing page.

That last step is the one no competing page ships, and it is the one that turns "my dual-GPU rig feels slow" into a diagnosis. Note that link width can also report low when a GPU is idling in a low-power state — check it under load, or run nvidia-smi -q -d PCI while a model is generating.

What to expect from each configuration, stated qualitatively because the quantitative public data does not exist:

• x8/x8, layer split: no meaningful penalty. This is the target configuration for consumer boards.
• x8/x8, tensor parallel: workable. Bandwidth is symmetric, which is what all-reduce cares about most.
• x16/x4, layer split: slightly longer model load on the x4 card, negligible effect on tokens per second.
• x16/x4, tensor parallel: the one to avoid. Asymmetric links mean every all-reduce waits on the narrow side, and the narrow side is a quarter of the width.

6. Slot Spacing and Physical Fit — The Boring Thing That Kills Builds

Slot count is not slot spacing. Most AIB RTX 5090 and 4090 cards occupy 3 to 3.5 slots, so two x16 positions need at least three slots of physical clearance or the upper card will thermally throttle against the lower card's backplate. A PCIe slot pitch is 20.32 mm, so "three slots of clearance" means roughly 61 mm between the two x16 positions — and a 3.5-slot card needs more than that before its fans have anywhere to breathe.

The RTX 4090 at $1,599–$1,999 and 450W of TDP is the classic offender: triple-slot open-air coolers designed on the assumption that nothing sits directly beneath them. Stack two of them two slots apart and the top card's intake fans are inhaling the lower card's exhaust from a 15 mm gap. You will see it as thermal throttling on GPU 0 within minutes of sustained load, and as a 10–20°C delta between the two cards at idle-to-load transition.

Four things to sort out before ordering:

• Count the gap on the board photo. Vendor product pages show the PCB; count slot positions between the two x16 slots, do not trust "supports 2-way multi-GPU".
• Prefer blower or 2-slot cards for stacked configurations. The used market still carries blower-style 3090s and 2-slot workstation cards for exactly this reason. Open-air triple-fan designs are built for a single-GPU case.
• Consider vertical or riser mounting for the second card. A PCIe 4.0-rated riser on a chipset x4 slot is perfectly adequate for layer-split inference — the bandwidth analysis above says so. For tensor parallelism, buy a Gen5-rated riser or skip the idea.
• Brace both cards. A 2kg triple-slot card cantilevered off a PCIe slot sags, and sag on the upper card closes the gap you just designed for. A support bracket per card is the cheapest insurance in the build — the Acer GPU Support Bracket in our workstation bundle below is a $15–$25 item that protects a $4,000 pair of cards.

Two stacked 350–575W cards also make noise a design problem rather than an afterthought. Our quiet AI PC guide covers airflow layouts that keep a dual-GPU box liveable in the same room as a person.

7. Power Delivery, ECC, and the Rest of the Spec Sheet

Sustained AI load is not gaming load. A gaming board's VRM sees minutes of peak draw between frame-rate dips; a dual-GPU inference box holds high draw for hours, and in a fine-tuning run, for days. That changes which board specs matter.

• VRM and heatsink mass. Prefer boards with genuinely large VRM heatsinks and a documented phase count over boards that advertise overclocking headroom. You are not chasing peak; you are chasing hours at 80% without thermal drift.
• Chipset M.2 lanes. Your model store — the drive holding fifteen GGUF checkpoints — does not need Gen5. Put it on a chipset M.2 socket and keep the CPU-fed socket for your working drive. Just check the lane-sharing table first, per section 5.
• ECC memory. Supported on TRX50 and WRX90 and worth having for multi-day fine-tuning runs, where a single bit flip silently corrupts a checkpoint. For inference, it is a nice-to-have: a corrupted token is a bad token, not a lost week.
• 24-pin and EPS headroom. Two GPUs mean two 12V-2x6 cables and a PSU that can absorb transient spikes from both at once. Dual-GPU power sizing has its own article — read the AI workstation PSU guide before you pick a wattage, because the answer is higher than the sum of the TDPs suggests.
• Running cost. Two 3090s at 350W each, plus platform, is a real electricity line item if the box runs continuously. We costed that out in the local AI electricity cost analysis.

8. Three Complete Builds, With the Board as the Anchor

Each build is anchored on its platform, with GPU pricing from our catalogue and wattage summed from vendor TDPs. Expected throughput ranges assume 4-bit quantized models under llama.cpp layer split.

Build A — The 48GB budget rig (~$2,000–$2,900 total)

Two used RTX 3090s at $699–$999 each give you 48GB of VRAM and 936 GB/s of bandwidth per card — still the best dollars-per-gigabyte in consumer AI in 2026. Pair them with an X870E board running x8/x8, a Ryzen 7 or 9, 64GB of DDR5, and a 1300W+ PSU.

• Board: X870E with confirmed x8/x8 bifurcation and 3+ slots of spacing, ~$300–$450
• GPUs: 2× RTX 3090, $1,398–$1,998
• System draw under load: ~950–1,050W peak (700W GPUs + platform + transients)
• Runs: DeepSeek R1 70B and Qwen 3 72B at 4-bit (~40–42GB), with room for KV cache at long context
• Expected: roughly 12–20 tok/s on a 70B at Q4 under layer split, higher on smaller models

The trade-off worth understanding: 3090s are PCIe 4.0 x16 cards, so bifurcating a Gen5 board gives them Gen4 x8 — ~16 GB/s each, which section 2 already established is ample. The honest alternative is one newer card; used RTX 3090 vs RTX 5070 Ti runs that comparison properly, and RTX 4090 vs RTX 3090 covers the step up. Our AI on a budget hub is the wider entry point for this tier.

Build B — The 32GB mid rig (~$1,400–$2,200 total)

Two RTX 5060 Ti 16GB cards at $429–$479 each is the cheapest credible dual-GPU entry: 32GB combined, Blackwell tensor cores with FP4 support, and just 150W per card — which means a mainstream PSU, a mainstream case, and no thermal drama even in a stacked configuration. The 128-bit bus caps each card at 448 GB/s, so this is a capacity play rather than a speed play.

For a single-card step up instead, a RTX 5080 at $999–$1,099 brings 960 GB/s and 16GB in one slot — faster per token, but no more capacity than one 5060 Ti pair member. RTX 5090 vs RTX 5080 and RTX 5060 Ti vs RTX 4060 Ti cover the tier boundaries.

• Board: mid-tier X870E or Z890 with x8/x8, ~$250–$350
• System draw under load: ~550–650W peak
• Runs: Llama 4 Scout 8B comfortably, 32B-class models at 4-bit with room to spare
• Who should skip it: anyone targeting 70B. 32GB does not hold a 70B at Q4 with usable context, and two mid cards will not fix that.

Build C — The no-compromise rig ($8,000–$14,000 total)

Two RTX 5090s at $1,999–$2,199 each on a WRX90 platform: 64GB of GDDR7, 1,792 GB/s per card, x16/x16 with 128 PCIe 5.0 lanes behind it, ECC registered DDR5 across eight channels, and headroom for two more cards later. This is the build where tensor parallelism under vLLM actually pays for itself, and where the lane count stops being a talking point and starts being a specification.

• Board: ASUS Pro WS WRX90E-SAGE SE class, seven PCIe 5.0 x16 slots, ~$1,100–$1,600
• System draw under load: ~1,500–1,700W peak (1,150W GPUs + a 350W-class Threadripper PRO + platform)
• Runs: Llama 4 Maverick 70B at 8-bit rather than 4-bit, or 70B-class models tensor-parallel with concurrent request serving
• The power warning: this build does not fit a standard US 15A/120V circuit. That circuit is rated 1,800W peak, but the NEC continuous-load rule derates it to 1,440W for anything running three hours or more — which is exactly what a sustained inference or fine-tuning job is. At ~1,500–1,700W of DC output you are drawing roughly 1,630–1,850W at the wall after conversion losses, over the continuous limit and brushing the peak rating. Your options are a dedicated 20A circuit, 240V mains, power-limiting both cards with nvidia-smi -pl, or splitting across two PSUs on two circuits — the PSU guide works through all four. Plan the circuit before the parts list.

RTX 5090 vs RTX 3090 quantifies what the price step actually buys, and the best consumer GPU for local LLMs ranks the wider field. If you want the full parts-and-assembly walkthrough rather than a BOM, our step-by-step AI workstation build covers it.

9. When NOT to Build a Dual-GPU Box

Three situations where the second slot is the wrong answer, and one of them applies to more readers than the affiliate roundups would like to admit.

One bigger card instead of two smaller ones

32GB on a single RTX 5090 beats 2× 16GB for most workloads, and it is not close. No split means no layer-boundary transfer, no engine configuration, no bifurcation research, no slot-spacing problem, no second power cable, and a 575W card instead of a 700W pair. The only thing the pair wins is raw dollars-per-gigabyte. The cheapest path to 32GB lays out every option including the used market.

A 128GB unified-memory box, if you want headroom rather than throughput

If the goal is running large MoE models at all rather than running mid-size models fast, a unified-memory machine changes the question. 128GB of shared memory holds models that a 48GB dual-GPU rig cannot touch, at lower bandwidth and a fraction of the power. The Strix Halo mini PC guide covers the AMD route, and DGX Spark vs Strix Halo the head-to-head.

NVIDIA PAIR, if you already own a second GPU machine

Announced at IFA on 3 September 2026, NVIDIA PAIR routes inference across separate machines on your local network. If there is already a GPU PC in the house, the second card may not need to go in your second slot at all — it can stay where it is. Our PAIR hardware guide covers what it needs and what it does not solve.

Or: stop building

If this article has been an accumulating list of things that can go wrong — lane-sharing footnotes, bifurcation settings, slot pitch arithmetic, circuit capacity — that reaction is information, not failure. A prebuilt workstation ships with the lane allocation already correct and the thermals already validated. Build vs buy for AI workstations runs the real numbers on that decision, and the best prebuilt AI workstations covers who to buy from.

The Verdict

Buy the board that matches your inference engine, not the board with the most lanes.

For the overwhelming majority of local-LLM builders — anyone whose stack is Ollama, LM Studio or llama.cpp — a $250–$450 X870E or Z890 board with confirmed x8/x8 bifurcation and three slots of spacing is the correct purchase, and the thousand-plus dollars saved against a Threadripper platform belongs in a second GPU. Read the manual's lane-sharing table before you order, not after. Verify the negotiated link width after the build with nvidia-smi.

Step up to TRX50 when you are running vLLM tensor-parallel workloads with concurrent requests, or when you need quad-channel memory for MoE offload. Step up to WRX90 when you are running four or more cards, fine-tuning for days at a time, or need ECC as a correctness requirement rather than a preference.

And if you take one thing from the counterintuitive part: PCIe width is not where your tokens per second live. Your tokens per second live in VRAM capacity and memory bandwidth. Start at the AI GPU buying guide hub to pick the cards, the local LLM hub to pick what you will run on them, and the multi-GPU setup guide to make two of them work together once the parts arrive.